1. Technical Field
The present invention is related to a parallel digital bus for transmitting data in a digital system. More specifically, the present invention relates to an apparatus and method for correcting a one-bit error occurring in the parallel digital bus so as to maintain the performance of the system.
2. Related Art
Contemporary apparatuses and methods for correcting errors occurring in data transmitted over a parallel digital bus are burdened by serious drawbacks. Specifically, when a one-bit error occurs in such data, the error cannot and is not effectively corrected under certain circumstances.
For example, as explained in more detail below, if an error bit is found, the arrangement checks for the existence of the error by utilizing the parity bit. If the bit error is temporary, the transmitter retries transmitting the data in a software method so as to maintain the performance, but the error cannot be corrected. Therefore, if a one-bit error occurred, the system cannot maintain normal operation.